1. Field of the Invention
The present invention relates to an internal clock generator for generating a clock, and more particularly to an internal clock generator which is utilized for an apparatus using a method for processing a signal based on a clock generated by itself (hereinafter referred to as a "self-timed method").
2. Description of the Background Art
An example of a self-timed apparatus is an information processor such as an arithmetic circuit. The self-timed apparatus comprises a clock generator for generating an internal clock (an internal clock generator) and a self-timed apparatus body for processing a signal based on the clock.
Two cases are caused by changing various conditions, for example, process conditions, a variation in manufacture, the ambient environment such as an ambient temperature, the transition of an input signal and the like. In a first case, the cycle of the generated clock fluctuates. In a second case, on a path provided between first and second specific nodes in the self-timed apparatus body, a delay time (processing time) required to input a signal to the first node, to process the signal on the path, and to output the processed signal to the second node fluctuates. The transition of the input signal means that the input signal is changed from the "H" level to the "L" level, and from the "L" level to the "H" level.
When at least one of the two cases is caused, the self-timed apparatus sometimes malfunctions. For example, in the case where the self-timed apparatus body has a structure in which a signal is fetched at the effective edge of the clock on the first node, the fetched signal is processed and the processed signal is fetched at the next effective edge on the second node, the malfunction of the self-timed apparatus is sometimes caused. In the case where the signal is processed synchronously with the clock, it is necessary to process the signal between the effective edges. If the signal cannot be processed between the effective edges, that is, a period for the effective edges is shorter than the processing time, the self-timed apparatus malfunctions.
Accordingly, it is necessary to design the self-timed apparatus to always make the period for the effective edges longer than the processing time such that a malfunction is not caused even if the conditions are changed.
However, it is insufficient that the difference between the period for the effective edges and the processing time (hereinafter referred to as an "operating margin") is simply increased so as to make the period for the effective edges longer than the processing time. As the operating margin is increased, the time for processing the signal by the self-timed apparatus becomes longer. Consequently, as the operating margin is smaller, the time for processing the signal by the self-timed apparatus is shortened.
As described above, it is necessary to always make the period for the effective edges longer than the processing time and to reduce the operating margin as much as possible in order to obtain a self-timed apparatus which does not malfunction due to the period of the clock and can process the signal in a short time.
However, it is difficult to decide the cycle of the clock such that the period for the effective edges is always longer than the processing time and the operating margin is always reduced as much as possible. The reason is that it is necessary to allow for a fluctuation in the cycle of the clock in the first case and a fluctuation in the processing time in the second case.
A method for diminishing the influence of conditions has been disclosed in "Design of a Free-Running Multiplier", Chapter V, (Technical Report of Institute of Electronics, Information and Communication Engineers of Japan (IEICEJ) "Integrated Circuit" ICD 93-83 to 93, p 7 to 14 by Mr. Yano). This method uses a part of a self-timed apparatus body for a delay element utilized to decide the cycle of a clock which is built in a clock generator. According to this method, it is pointed out that problems are caused in three cases, that is, a case (1) where a path is changed by an input, a case (2) where a circuit is complicated, and a case (3) where a path having a maximum processing time is changed on the ambient environment conditions. The case (1) includes a case (4) where the processing time is varied depending on the transition of an input signal.
The case (4) will be described below in detail. FIG. 19 is a block diagram showing the structure of a clock generator according to the prior art. FIG. 20 is a timing chart for each signal on nodes n4, di and n5 shown in FIG. 19. A clock control circuit G01 has the same delay time in the cases where an input signal is changed from the "H" level to the "L" level, and from the "L" level to the "H" level. The clock control circuit G01 has a delay time Tde. First of all, an enable signal on the node n4 is changed from the "L" level to the "H" level. Then, a signal on the node di is changed from the "H" level to the "L" level after the delay time Tde of the clock control circuit G01. Thereafter, a signal on the node n5 is changed from the "H" level to the "L" level after a delay time Tdn of a delay circuit D'. Subsequently, the signal on the node di is changed from the "L" level to the "H" level after the delay time Tde of the clock control circuit G01. Then, the signal on the node n5 is changed from the "L" level to the "H" level after a delay time Tdp of the delay circuit D'. Thereafter, the signal on the node di is changed from the "H" level to the "L" level again after the delay time Tde of the clock control circuit G01. By repeating the above-mentioned operation, an internal clock is generated on the node n5.
A time width TdL for a period having the "L" level of the clock on the node n5 (hereinafter referred to as a "Low period") is the sum of the delay times Tdp and Tde. A time width TdH for a period having the "H" level of the clock on the node n5 (hereinafter referred to as a "High period") is the sum of the delay times Tdn and Tde. Accordingly, the duty ratio of the clock (the delay time TdH: the delay time TdL) depends on the difference between the delay times Tdn and Tdp. If the delay time TdL is not equal to the delay time TdH, the duty ratio (TdH/TdL) is not 50%.
It is supposed that the duty ratio is not 50% and both edges are effective ones. As an example of this case, the delay time TdL is longer than the delay time TdH. In this case, short and long intervals are repeated so that the effective edges are produced. Accordingly, in the case where the self-timed apparatus body processes a signal based on the timings of both edges of the clock, the signal can be processed between the effective edges before and after the delay time TdL but cannot be processed between the effective edges before and after the delay time TdH in some cases. In these cases, the self-timed apparatus malfunctions. In order not to cause such a malfunction, a delay element which generates a delay of .vertline.Tdn-Tdp.vertline. is inserted immediately after the delay circuit D', for example. Consequently, the time width between the effective edges having the short interval becomes equal to the delay time TdL. Thus, the malfunction can be eliminated. However, the time width between the effective edges having the long interval is further increased by the delay element, that is, the operating margin is increased so that the time for processing the signal by the self-timed apparatus becomes longer.
The case (3) will be described below in detail. In the case (3), a phenomenon is simpler than in the case (4). However, a bad effect is produced even in the case where it is not necessary to set the duty ratio to 50%. Therefore, the problem becomes serious. Only paths (critical paths) D1, D2, D3, D4 and D5 have the maximum processing times produced on the different ambient environment conditions, respectively. The delay time of the delay circuit D' shown in FIG. 19 is set equal to the processing time of the path D1. If the ambient environment conditions correspond to the path D1, there is no problem. However, if the ambient environment conditions correspond to the paths D2 to D5, a signal cannot be processed between the effective edges in some cases. In these cases, the self-timed apparatus malfunctions. Accordingly, a delay element which produces a delay having the greatest value of .vertline.Td1-Td2.vertline., .vertline.Td1-Td3.vertline., .vertline.Td1-Td4.vertline. and .vertline.Td1 -Td5.vertline. is inserted immediately after the delay circuit D', for example. Consequently, the time width between the effective edges becomes longer than the processing time so that a malfunction is eliminated. However, in the case where the ambient environment conditions correspond to the path D1, the operating margin is increased. Consequently, the time for processing the signal by the self-timed apparatus is increased.